Initial PIC32 state?

Created Fri, 27 May 2011 05:36:08 +0000 by djdesigns

djdesigns

Fri, 27 May 2011 05:36:08 +0000

Is there a document or code somewhere that documents the state of the PIC32 processor upon entry to the setup routine? This puppy is a wee bit more complex than the 8-bit ATMEL parts...

dattaway

Sat, 28 May 2011 06:13:47 +0000

Is there a document or code somewhere that documents the state of the PIC32 processor upon entry to the setup routine? This puppy is a wee bit more complex than the 8-bit ATMEL parts...

After the reset or after the bootloader?

I'm looking at the PIC32 reference manual, chapter 2.16, CPU Initialization, and 2.17, Effects of a Reset.

http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2612

Mark

Sat, 28 May 2011 15:04:25 +0000

This is kind of a long answer and you need to be familiar with PIC32 programming to understand it.

Below is the config bits from the bootloader. The bootloader gets run first and it really controls everything. Below that is the init code that gets called BEFORE setup(). By default, support for the Real Time Clock is disabled (RTC)

//************************************************************************
//*	These config bits are common to all CPUS

//*	Oscillator Settings
#pragma config	FNOSC		=	PRIPLL		// Oscillator selection
#pragma config	POSCMOD		=	XT			// Primary oscillator mode
#pragma config	FPLLIDIV 	=	DIV_2		// PLL input divider
#pragma config	FPLLMUL		=	MUL_20		// PLL multiplier
#pragma config	FPLLODIV 	=	DIV_1		// PLL output divider
#pragma config	FPBDIV		=	DIV_8		// Peripheral bus clock divider

// #pragma config FSOSCEN = ON // Secondary oscillator enable

//*	Clock control settings
#pragma config	IESO		=	OFF			// Internal/external clock switchover
#pragma config	FCKSM		=	CSDCMD		// Clock switching (CSx)/Clock monitor (CMx)
#pragma config	OSCIOFNC	=	OFF			// Clock output on OSCO pin enable

//*	Other Peripheral Device settings
#pragma config	FWDTEN		=	OFF			// Watchdog timer enable
#pragma config	WDTPS		=	PS1024		// Watchdog timer postscaler

//*	Code Protection settings
#pragma config	CP			=	OFF			// Code protection
#pragma config	BWP			=	OFF			// Boot flash write protect
#pragma config	PWP			=	OFF			// Program flash write protect

//*	Debug settings
#pragma config	ICESEL		=	ICS_PGx2	// ICE pin selection

// #pragma config DEBUG = OFF // Debug mode select

#if defined(32MX320F064H) || defined(32MX320F128H) || defined(32MX360F512L) //************************************************************************ //* PIC32MX3XX Configuration Settings //************************************************************************

//*	Oscillator Settings
#pragma config	FSOSCEN		=	ON			// Secondary oscillator enable


//*	Other Peripheral Device settings

//************************************************************************

#elif defined(32MX795F512L) //************************************************************************ //* PIC32MX7XX Configuration Settings //************************************************************************

//*	Oscillator Settings
#pragma config	FSOSCEN		=	OFF			// Secondary oscillator enable


//*	Other Peripheral Device settings

// #pragma config FSRSSEL = PRIORITY_0 // SRS interrupt priority #pragma config FSRSSEL = PRIORITY_7 // SRS interrupt priority #pragma config FCANIO = OFF // Standard/alternate CAN pin select (OFF=Alt) #pragma config FETHIO = ON // Standard/alternate ETH pin select (OFF=Alt) #pragma config FMIIEN = OFF // MII/RMII select (OFF=RMII)

//*	USB Settings
#pragma config	UPLLEN		=	ON			// USB PLL enable
#pragma config	UPLLIDIV	=	DIV_2		// USB PLL input divider
#pragma config	FVBUSONIO	=	OFF			// VBUS pin control
#pragma config	FUSBIDIO	=	OFF			// USBID pin control

//************************************************************************

#elif #warning CPU config bits not set for this CPU #endif

================================================================ //************************************************************************ void init() {

#ifdef ENABLE_PIC_RTC // Configure the device for maximum performance but do not change the PBDIV // Given the options, this function will change the flash wait states, RAM // wait state and enable prefetch cache but will not change the PBDIV. // The PBDIV value is already set via the pragma FPBDIV option above.. __PIC32_pbClk = SYSTEMConfig(F_CPU, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); #else __PIC32_pbClk = SYSTEMConfigPerformance(F_CPU); #endif

OpenCoreTimer(CORE_TICK_RATE);

// set up the core timer interrupt with a prioirty of 2 and zero sub-priority
mConfigIntCoreTimer((CT_INT_ON | CT_INT_PRIOR_2 | CT_INT_SUB_PRIOR_0));

// enable multi-vector interrupts
INTEnableSystemMultiVectoredInt();

#ifdef ENABLE_PIC_RTC RtccInit(); // init the RTCC // while(RtccGetClkStat() != RTCC_CLK_ON); // wait for the SOSC to be actually running and RTCC to have its clock source // could wait here at most 32ms

delay(50);
// time is MSb: hour, min, sec, rsvd. date is MSb: year, mon, mday, wday.
RtccOpen(0x10073000, 0x11010901, 0);
RtccSetTimeDate(0x10073000, 0x10101701);
// please note that the rsvd field has to be 0 in the time field!

#endif

//*	as per Al.Rodriguez@microchip.com, Jan 7, 2011
//*	Disable the JTAG interface.
DDPCONbits.JTAGEN	=	0;

#if defined (BOARD_MEGA) //* Turn Secondary oscillator off //* this is only needed on the mega board because the mega uses secondary ocsilator pins //* as general I/O { unsigned int dma_status; unsigned int int_status;

	mSYSTEMUnlock(int_status, dma_status);
	OSCCONCLR	=	_OSCCON_SOSCEN_MASK;
	mSYSTEMLock(int_status, dma_status);
}

#endif

}