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Stray Capacitance

Created Thu, 13 Feb 2014 08:53:53 +0000 by cobusmetnc


Thu, 13 Feb 2014 08:53:53 +0000

Hi all

I am trying to measure two signals and perform a fft to extract the necessary info. to calculate the impedance. The two signals are the source voltage which is PWM signal and that voltage divided by two resistors connected to ground.(see picture) [attachment=0]Picture1.png[/attachment] Problem is it looks like my voltage divided signal has gone through a capacitor and something in my sub-conscience is telling me it may be stray capacitance. Could anybody help with some tips or hints as to how to get rid or reduce this effect. It is cardinal for me to calculate a very accurate impedance. Sampling frequency is 500kHz Signal frequency will vary from 1kHz to 200kHz

Jacob Christ

Thu, 13 Feb 2014 20:53:03 +0000

Are you taking into consideration the cap in the sample and hold circuit in the uC? Also I have fooled myself in the past by putting my signal on the wrong adc pin and was coupling the signal intothe aadjacent pin where the sampling was really occurring.



Fri, 14 Feb 2014 06:11:47 +0000

if you lowered the resistance, how does that change the measurements?


Tue, 18 Feb 2014 09:23:01 +0000

The max source impedance at the analog input shall be a few kiloohms or less (see the datasheet), in order the S/H works properly. The stray capacitance with good wiring is something like 5pF. I do not know what your expectations are with the measurement design, but keep in mind the ADC channels A7 and A6 do not sample the inputs simultaneously. So PWM signal source and actual measurements of voltages at above points are off sync.


Thu, 20 Feb 2014 22:21:10 +0000

Thank you all for your input it has helped me tremendously. I am reiterating my circuit design and I am also going to take into account the sampling lag.

hdphilip could you maybe elaborate why high impedance will alter the reading. Is it because it increases the time constant together with the capacitor? Also I have to use the shown resistor, so will a op-amp voltage buffer solve the high impdance conundrum?

Thank you all once again


Thu, 20 Feb 2014 22:31:30 +0000

There's two impedance factors that affect the readings. From the ADC manual data sheet:

For the ADC module to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The analog output source impedance (RS), the interconnect impedance (RIC), and the internal sampling switch (RSS) impedance combine to directly affect the time required to charge the CHOLD . The combined impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. After the analog input channel is selected (changed), this acquisition function must be completed prior to starting the conversion. The internal holding capacitor will be in a discharged state prior to each sample operation.

Also, you can think of the ADC's impedance as being a resistor in parallel with the lower leg of your voltage divider, basically lowering the resistance of that leg. If your resistor is of the same order as the ADC impedance the resistance shift will be large. Thus, you should always try and have your input impedance at a bare minimum of 10x lower than the ADC impedance, if not better (100x lower).

From the PIC32MX7xx data sheet:

Recommended Impedance of Analog Voltage Source: 5KΩ

While the actual impedance isn't specified, from that value I'd expect it to be in the order of 500KΩ (perhaps someone in MCHP can clarify that value?)

Assuming it is 500KΩ, your voltage divider would effectively have a lower resistor of (1 / ((1/100,000) + (1/500,000))) = 83.3KΩ

And yes, buffering will help.


Thu, 03 Apr 2014 20:09:37 +0000

Here is some info from the PIC32 Applications group, regarding the ADC impedance:

The static input impedance on any ANx pin looking into the PIC32 part is ≥ 3.6Meg. It would be even higher if it was not for the multi-purpose multiplexed digital I/O logic functions that share the same pin.

While the ADC channel is actively “sampling”, charging the internal holding cap of the sample and hold, the internal series charging source impedance is ~3.25K Ohms looking into a 4.4pf series cap.

The data sheet RIN ≤ 5K, (i.e. “Recommended Impedance of Analog Voltage Source), is the maximum external source impedance of the voltage source permitted to guarantee meeting the minimum TSAMP and corresponding maximum “FCNV” , (i.e. Throughput Rate of the ADC). If the external Analog Voltage Source impedance is >5k then the user would need to increase the sample time TSAMP > TSAMP(min spec) accordingly to compensate for the increased RC charging time of the internal Sample/hold cap due to the higher analog source impedance. Increasing TSAMP obviously decreases the ADC throughput rate as well.

FYI: Data Sheet FCNV max is an absolute speed limit, decreasing the analog source impedance <5k does not permit the ADC to run faster it only guarantees that you can run up to the max FCNV and min TSAMP.



Mon, 07 Apr 2014 20:38:50 +0000

Additional comments from our Applications engineer:

After seeing his circuit on the forum and assuming he is trying to convert nodes A06 & A07 using the ADC and an FFT to calculate the unknown impedance between node A07 and ground, knowing at least R1 = 100k then I would offer this additional advice.

Customers setup: o PWM 1Khz -> 200Khz o ADC sample rate 500Khz

Issue #1: For an FFT the ADC sample rate should be a minimum of 4x the PWM frequency, preferably 10x instead of 2.5x @200Khz.

Issue #2: With (2) ANx inputs the total max bandwidth available is FCNV(max) / #analog inputs = 1msps/2 = 500Ksps which the user is already at. No more gas left so 2.5x PWM(max) is the top end but less than the 4x minimum I would recommend for FFT data.

Issue #3: For node A07, the effective source impedance is 20x greater than the 5K max ohm spec for 1msps operation and I’m sure at least 10x greater than required for 500ksps operation. So the user would need to increase the sample time significantly for the R1 100k ohm source impedance presented by node A07 which unfortunately would also decrease the throughput rate, FCNV, significantly from his present 500ksps. Otherwise the A07 node conversion results will be corrupted, incomplete and represent only a portion of the actual value, probably only the upper 5-6 bits with the lower remaining bits being un-deterministic at 500ksps.

A simpler way: I don’t have a lot of details and probably don’t fully understand the usage model but assuming the goal is to simply measure the resistance of one of the elements in the voltage divider depicted below there is a simpler way than using an FFT transform. From the circuit diagram given I can only deduce that the load is a simple resistive load. If so, then configure the PWM for 100% duty cycle or as a standard I/O output pin driving a logic high. You will need to do this so you can effectively increase the ADC sample time to accommodate the reduced ADC internal sample cap charging current limited by the large 100k R1. You must sample long enough, (i.e. ~2.5us), for the sample/hold cap to charge before triggering the conversion.

Another Alternative Method: (Doesn't require any intervention of the users PWM signal) Configured the ADC as: AD1CON1<SSRC> = 000b AD1CON1<ASAM> = 1 AD1CON2<CSCNA> = 1; Scan mode ANx inputs for nodes A07 and A06 AD1CON2<SMPI> =0001b; interrupt after both A07 and A06 nodes measured AD1CON2<VCFG> = 000b

You could use the following technique as a back round task:

  1. Configure a timer(x) period for 2.5us period and enable it’s interrupt. (do not start)

  2. Connect the PWM to the PIC32 pin INT0 external interrupt as well as A06 to trigger an INT0 interrupt on the rising edge of the PWM. (Do not enb INT0 until you want to do an impedance measurement) The Idea here using the INT0 is to synchronize the start of the PWM high time to the ADC sampling cycle since I don’t know the source of the PWM signal. If the PWM output is being generated by one of the PIC32 “Output Compare modules” then depending of the mode, one could use the output compare interrupt in place of the INT0 interrupt. Remember the ADC is always sampling the connected ANx input pin until the conversion trigger.

  3. When needed to measure the impedance, clear the INT0 IFSx flag and enable the INT0 interrupt. a) Inside the INT0 interrupt service routine clear INT0 IFSx flag, set timer(x) = 0x0000, and then set timer(x) TON bit, start PIC32 timer(x) to generate a timer interrupt after 2.5us then return.

  4. Inside timer(x) interrupt service routine: a) Clear timer(x) IFSx flag b) Read the state of the INT0 pin. i. If INT0 pin is a logic high then clear AD1CON1<SAMP>=0 to end sampling and start ADC conversion and stop timer(x), TON=0, and return (Valid measurement) ii. If INT0 pin is a logic low then stop timer(x), TON=0, and return. Leave INT0 interrupt enabled so back round task will continuously run until successful impedance measurement conditions meet. (i.e. until PWM duty cycle high time >= 2.5us)

  5. Inside ADC interrupt service routine disable INT0 interrupt, stop timer(x) TON=0. a) If AVDD = 3.3v and Unknown Impedance = Rx between node A07 and AVSS (ground) b) Read A07 and A06 from ADC results buffer and process accordingly i. A06 Volts = ((ADC A06 result * 3.3)/1024) ii. A07 Volts = ((ADC A07 result * 3.3)/1024) iii. Unknown Impedance Rx = (A07 volts * R1) / (A06 volts - A07 volts)